The present invention relates to a semiconductor memory device and a method for manufacturing the same, and more particularly, to a capacitor of a semiconductor memory device having a cylindrical storage electrode composed of a selective hemispherical grained silicon layer and a method for manufacturing the same.
As the integration density of semiconductor memory devices, such as a dynamic random access memory DRAM increases, the area occupied by a unit cell consisting of a transistor and a cell capacitor is gradually decreased. A decrease in cell capacitance due to a decrease in the area of a memory cell seriously restricts the integration density of the DRAM. The decrease in cell capacitance further deteriorates the ability to read data from the memory cell, increases soft error rate, hinders the operation of a device in a low voltage state, and deteriorates a refresh characteristic, thus increasing consumption of currents. Therefore, problems caused by the decrease in cell capacitance should be solved in order to obtain high density semiconductor memory device integration.
There are methods for forming a dielectric film using a material having a high dielectric constant and for forming a thin dielectric film, in order to increase the cell capacitance. However, the method for forming the dielectric film with a material having a high dielectric constant generally has the problems that leakage currents are large and breakdown voltage is low, and the method for forming the thin dielectric film deteriorates the reliability of the semiconductor device by increasing the leakage currents.
Therefore, a method for increasing the capacitance by increasing the surface area of the capacitor electrode was suggested. As a representative example, it is possible to easily increase the surface area of a lower electrode if an HSG silicon layer having hemisphere-shaped grains is selectively formed on the lower electrode surface to improve the capacitance thereof.
FIGS. 1 to 3 are sectional views for explaining the method for selectively forming the HSG silicon layer only in the lower electrode of the capacitor of the semiconductor memory device according to a conventional technology.
Referring to FIG. 1, an insulating film, for example, an oxide film 3 is formed on a semiconductor substrate 1 and patterned to form a contact hole h.sub.1 which exposes a predetermined area of the semiconductor substrate 1.
Referring to FIG. 2, an amorphous silicon is deposited on the resultant structure shown in FIG. 1 to form a conductive layer 5 filling the contact hole h.sub.1.
Referring to FIG. 3, a lower electrode 7 for covering the contact hole h.sub.1 is formed by patterning the conductive layer 5 and an HSG silicon layer 9 is formed on the surface of the lower electrode 7. In this case, the lower electrode 7 should be in an amorphous state and the impurity concentration thereof should be increased to reduce a resistance thereof.
However, when the impurity concentration of the lower electrode 7 is increased, impurities are diffused into the semiconductor substrate 1 contacting the lower electrode 7. Accordingly, the impurity concentration of the semiconductor substrate 1, namely, a source area or a drain area thereof is changed, thus deteriorating the characteristic of the transistor.
As mentioned above, the impurity concentration of the source and drain areas of the semiconductor substrate 1 is directly affected by the impurity concentration of the lower electrode 7. Therefore, the lower the impurity concentration of the lower electrode 7, the less amount of change of the impurity concentration of the source and drain areas during a following thermal process. However, when the impurity concentration of the lower electrode 7 is reduced, a phenomenon occurs in a MOS capacitor structure, namely, the phenomenon in which the capacitance changes according to the magnitude of a voltage applied to the electrode of the capacitor occurs. Especially, in the capacitor structure in which the HSG film 9 is formed on the surface of the lower electrode 7, the amount of change of the capacitance increases more than in a general capacitor structure without the HSG film 9. This is because depletion layers formed in the hemisphere-shaped grains constituting the HSG film 9 overlap each other, which increases the width of an actual depletion layer. When such a phenomenon occurs, a minimum capacitance Cmin and a maximum capacitance Cmax exist within a certain voltage range since the capacitance changes according to the voltage applied to the electrode of the capacitor.
FIG. 4 is a graph showing the change of Cmin and Cmax according to an impurity doping concentration when an HSG layer is formed on a lower electrode of the capacitor and when an HSG layer is not formed thereon.
In FIG. 4, phosphorus (P) is used as the impurity which is doped in the lower electrode. Here, Cmin/Cmax obtained when no HSG layer is formed on the surface of the lower electrode, represented as (.box-solid.), is compared with that obtained when an HSG layer, represented as (.circle-solid.), is formed thereon, under the condition that PH.sub.3 is used as a phosphorus source gas and the flow rate thereof is changed to 5, 7,and 15 sccm, respectively. While Cmin/Cmax is sharply lowered as the flow rate of the PH.sub.3 is reduced when the HSG layer is formed on the surface of the lower electrode, Cmin/Cmax are not sharply lowered in spite of the change in the flow rate of the PH.sub.3, when no HSG layer is formed.
According to the above result, it is necessary to form a lower electrode having a new structure in which Cmin/Cmax are not reduced when an HSG layer is formed on the lower electrode surface.